What is northbridge, southbridge, how northbridge, southbridge works?

Northbridge and Southbridge are chip sets that handle communications functions on most PC type motherboards. Northbridge is also known as a MCH, memory controller hub, or an IMC, integrated memory controller, in Intel systems, AMD, VIA, SiS and other motherboard. Separating the chipset into the northbridge and southbridge is common, although there are rare instances where these two chips have been combined onto one die when design complexity and fabrication processes permit it.
The Northbridge is a controller chip that handles interaction among the CPU, RAM, the L2 or Level 2 cache, BIOS ROM, and PCI Express, and the AGP, Accelerated Graphics Port. The components that benefit most from fast communication with the processor, in other words. It uses the FSB, fast Front Side Bus, to link the various components. Some northbridges also contain integrated video controllers, also known as a GMCH, Graphics and Memory Controller Hub, in Intel systems. Because different processors and RAM require different signalling, a northbridge will typically work with only one or two classes of CPUs and generally only one type of RAM.

The northbridge plays an important part in how far a computer can be overclocked, as its frequency is used as a baseline for the CPU to establish its own operating frequency. This chip's temperature typically increases as processor speed becomes faster, requiring increased cooling measures. CPUs cannot be overclocked infinitely, as digital circuits are limited by physical factors such as propagation delay which increases with (among other factors) operating temperature, therefore most overclocking applications have software limitations which limit the multiplier and external clock setting.

The southbridge, also known as an ICH, I/O controller hub, in Intel systems, AMD, VIA, SiS and other motherboard, is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access.

Because the southbridge is further removed from the CPU, it is given responsibility for the slower devices on a typical microcomputer. A particular southbridge will usually work with several different northbridges, but these two chips must be designed to work together; there is no industry-wide standard for interoperability between different core logic chipset designs. Traditionally this interface between northbridge and southbridge was simply the PCI bus, but since this created a performance bottleneck, most current chipsets use a different (often proprietary) interface with higher performance.

The Southbridge handles more basic, slower, forms of I/O, such as serial ports, USB ports, and IDE. The Southbridge is attached to the Northbridge's PCI bus.

The Northbridge-Southbridge chips enormously speed up modern computers. They are used by VIA and AMD chipsets as well as some Intel chip sets, so they are what you will find on almost all current computers. The Northbridge-Southbridge combination represents a basic minimum architecture for a modern computer and you'd be hard put to find one that doesn't use them.

The exceptions are computers that use Intel's new IHA, Intel Hub Architecture. Like Northbridge-Southbridge, IHA uses two chips, called hub controllers, to handle communications between the processor and the other system components. However, the GMCH, Graphics and AGP Memory Hub, the equivalent of the Northbridge, doesn't handle the PCI bus. That is now handled by the ICH, I/O Controller Hub, which sits on a bus and is twice as fast as the Southbridge's bus. More importantly, the IHA bus can detect different data types as they move over the bus and optimize bus performance for the kinds of data being handled.